The present invention relates generally to Electronic Computer-Aided Design (ECAD). More specifically, it pertains to a system and methodology of using analog standard cells, and an analog standard cell library, in a System-on-Chip (SoC) physical design environment. What is taught is a definition of both general and specialized analog standard cells that permit the physical layout of analog and mixed-signal SoCs to be designed quickly and efficiently using ECAD tools.
While the term analog standard cells exists in prior art, prior art does not define analog standard cells in a manner that accords them significant utility in designing the physical layout of analog or mixed-signal SoCs. Specifically, prior art has not taught analog standard cells comprising relatively simple functions, predetermined cell heights, inclusion in a library of analog standard cells, and utilization by ECAD tools to enable the fast and efficient layout of relatively complicated functions out of such relatively simple analog standard cells. Furthermore, prior art does not describe, in part or in whole, a general analog standard cell as is taught as one feature of the present invention.
A common methodology of designing analog and mixed-signal SoCs is to use pcells. A pcell, short for parametric cell, is an analog circuit cell that has one or more parameters that may be varied within a specified range by a designer. For example, a simple pcell is a single-transistor cell, which may have as exemplary variable parameters the contact spacing or diffusion width. This enables a very flexible analog cell that may be used as a building block for more complex analog circuits in an SoC. However, because it is advantageous to maximize analog circuit performance by minimizing layout area, routing, parasitics, etc., varying such parameters in a pcell typically alters its overall dimensions. Such fine-grain variation of a pcell's outside dimensions generally results in pcells whose heights are not integer multiples of each other. For example, a first pcell may have a height of 1 unit and a second pcell may have a height of 1.13 units—such heights obviously not integer multiples of each other. This is in contrast to integer-multiple heights, for example a first pcell with height of 1 unit and a second pcell with height of 2 units.
Pcells with such non-integer-multiple dimensions (variable width and/or height) are extremely difficult to efficiently place within an SoC physical design. Most significantly, the non-integer-multiple pcell heights preclude pcells from being placed-and-routed by ECAD tools, which rely on fixed-height or integer-multiple-height cells.
Accordingly, what is desired, and has not heretofore been developed, is a system and methodology to layout the physical design of analog and mixed-signal SoCs rapidly and efficiently using ECAD tools. In the subsequent sections it will be shown how the specific definition of analog standard cells, the various exemplary types of analog standard cells, and the analog standard cell library enables such rapid and efficient layout of SoCs physical designs using ECAD tools.
Terminology used in this application, unless otherwise defined, shall derive its meaning within the scope and context accorded by the fields of ECAD, Very Large Scale Integration (VLSI), analog-, digital-, and mixed-signal circuit design, and the like.